Receiver for a switched signal on a communication line

ABSTRACT

A receiver for receiving a switched signal on a communication line ( 1 ), such as a LIN bus, the signal varying between first and second voltage levels (sup, ground). The receiver comprises a comparator ( 31,54 ) responsive to the relative values of the received signal voltage level (Vlin) and an input reference voltage level (Vsup). The comparator ( 31, 54 ) comprises a current generator ( 40,41 ) selectively operatble when the recieved signal is asserted to produce an input current (Iin) which is a function of the received signal voltage level (Vlin) and a reference current (Isup) which is a function of the input reference voltage level (Vsup), and output means ( 28, 32, 31; 55, 56 ) responsive to the relative values of the input current (Iin) and the reference current (Isup). The output means ( 28, 32, 31; 56 ) is supplied with power at a voltage (VDD) substantially lower than the difference bwtween the first and second voltage levels (Vsup, ground). A switch ( 26, 35, 46 ) responsive to the input current (Iin) reduces the power consumption of the comparator when the received signal is de-asserted.

FIELD OF THE INVENTION

This invention relates to a receiver for a switched signal on acommunication line.

BACKGROUND OF THE INVENTION

Local networks often make use of a communication line, such as acommunication bus, over which a set of nodes communicates. A drivermodule in a master node applies power to the line, the driver modulebeing switched to produce step changes in the power in the line totransmit signals to receivers in remote slave nodes over the line. Theswitched power signal activates the multiplexed remote nodes connectedto the line and the line also selectively transmits signals from theremote nodes back to a central processing unit.

Such a bus is used in automotive vehicles, for example, the buscomprising either a single line or a twisted pair of conductors in whichthe current flows, the close coupling between the pair of conductorsreducing their sensitivity to electromagnetic interference (‘EMI’), thatis to say reception of noise induced in the wires of the bus, andimproving their electromagnetic compatibility (‘EMC’), that is to saythe radiation of parasitic fields by the currents flowing in the wiresof the bus; both are critical parameters, especially in automotiveapplications.

Historically, in automotive applications, functions such as door locks,seat positions, electric mirrors, and window operations have beencontrolled directly by electrical direct current delivered by wires andswitches. Such functions may today be controlled by ECUs (ElectronicControl Units) together with sensors and actuators in a multiplexedController Area Network (CAN). The Controller Area Network (CAN)standard (ISO 11898) allows data to be transmitted by switching avoltage, at a frequency of 250 kbauds to 1 Mbaud for example, to themultiplexed receiver modules over the twisted pair cable. The receivermodules may be actuators that perform a function, for example bygenerating mechanical power required, or sensors that respond toactivation by making measurements and transmitting the results back tothe ECU over the bus.

The CAN bus was designed to be used as a vehicle serial data bus, andsatisfies the demands of real-time processing, reliable operation in avehicle's EMI environment, is cost-effective, and provides a reasonabledata bandwidth. However, connecting with the main body network directlyvia a CAN bus system can be expensive because of increased costs pernode and because high overall network traffic can make managementextremely difficult. To help reduce costs, the logical extension is tostructure the network hierarchically.

A variant on the CAN standard is the LIN (Local Interconnect Network)sub-bus standard (see ISO 7498), which is an extension to the CAN bus,at lower speed and on a single wire bus, to provide connection to localnetwork clusters. A LIN sub-bus system uses a single-wire implementation(enhanced ISO9141), which can significantly reduce manufacturing andcomponent costs. Component costs are further reduced byself-synchronization, without crystal or ceramics resonator, in theslave node. The system is based on common Universal asynchronousreceiver and transmitter serial communications interface (UART/SCI)hardware that is shared by most micro-controllers, for a more flexible,lower-cost silicon implementation.

The wires of a communication bus or similar line are often long andpresent a substantial distributed reactive load to the transmitter towhich they are connected and especially their capacitive loads may beindividually variable. The distributed impedance gives the wave frontsof a nominally rectangular switched pulse a finite slew rate. It isaccordingly important for the receiver to respond at an accuratelyrepeatable signal level in order to ensure accurate timing of thereceiver response. This is important for a CAN bus and other systems butthe self-synchronisation feature of a LIN system makes it especiallyimportant for the response level of a LIN receiver to be precise.

It is also important for the standby current of the nodes of the systemto be very low, especially where such systems are powered by a batteryor accumulator. Accordingly, the nodes of the system have standby modesof operation, in which current consumption is reduced but it is alsodesirable for the wake-up time, that is to say the time taken to passthe node from the standby to the operational mode to be short. Inaddition, cost considerations are important and make it desirable forcomponents of the nodes to use as small an area of silicon as possible;it follows that it is preferable to avoid including extra receivercomponents to detect the signal front and wake up main receiver elementsin the node.

U.S. Pat. No. 6,281,714 discloses a differential receiver circuit forcomputer and other information processing systems but does not disclosea receiver for a communication bus system enabling standby current of anode of the system to be reduced.

SUMMARY OF THE INVENTION

The present invention provides a receiver for receiving a switchedsignal on a communication line as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a typical LIN bus installation to whichthe present invention may be applied,

FIG. 2 is a schematic diagram of a known receiver for a LIN bus,

FIG. 3 is a diagram of signals appearing in operation of the LIN businstallation of FIG. 1,

FIG. 4 is a schematic diagram of a receiver for a LIN bus in accordancewith one embodiment of the invention, given by way of example,

FIG. 5 is a diagram of signals appearing in operation of the receiver ofFIG. 4,

FIG. 6 is a diagram showing the receiver of FIG. 4 in more detail, and

FIG. 7 is a schematic diagram of a receiver for a LIN bus in accordancewith another embodiment of the invention, given by way of example

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred application for the invention is to a LIN bus. FIG. 1 showsthe overall structure of a typical LIN bus which is a communication line1 carrying switched signals, the protocol of which defines data bytes,security and error detection. The LIN bus comprises a single wire with asingle channel and is connected to nodes such as 2, 3, 4 and 5, one ofwhich is a master node capable of transmitting and receiving and theother nodes are slave nodes capable only of receiving. All nodes includea slave communication task that is split into a transmit and a receivetask, while the master node includes an additional master transmit task.The slave nodes are synchronised without crystal or ceramics resonatorsin the slave nodes. While this application to a LIN bus is a preferredapplication of the invention, it will be appreciated that the inventionis also applicable to other communication lines.

FIG. 2 shows a known receiver in a node (master or slave) for a LIN bus.The bus supplies an input signal to a terminal 7, which is connected toa low pass filter 8 that removes radio frequency interference. Thefiltered signal is supplied to a first receiver 9 and a second receiver10. The first receiver 9 responds with relatively low accuracy to areduction in the voltage at the terminal 7 corresponding to the arrivalof a wave front of a pulse. The first receiver 9 is permanentlyenergised and operational, even in the standby mode of the node. Itoperates with a low quiescent current. The second receiver 10 has oneinput connected to receive the signal from the LIN terminal 7 and asecond input connected to the junction between 2 resistors 11 and 12,connected in series between a positive supply terminal 13 and ground 14to form a voltage divider. The output of the receiver 10 is connected toa node output terminal 15 and is activated and deactivated by a monitor16.

In operation, when the first receiver 9 detects the beginning of a pulseat the LIN terminal 7, the monitor 16 activates the main receiver 10,which compares the signal from the voltage divider formed by resistors11 and 12 and asserts a signal on the output terminal 15 at the momentwhen the signal from the filter 8 drops below the reference voltage. Thesignal levels are illustrated in FIG. 3, where the signal from thefilter 8 is shown at 16, the reference threshold voltage defined by thevoltage divider 11 and 12 is shown at 17 and the output signal at thenode output terminal 15 is shown at 18. When the voltage from the filter8 exceeds the voltage from the voltage detector 11, 12 again, the secondreceiver 10 re-asserts the pulse on the output terminal 15 and when thesignal from the filter 8 reaches the de-assert level and stays there forlonger than the length of a code frame, the monitor 16 reactivates thesecond receiver 10. The second receiver 10 can be designed with a higherquiescent current than the first receiver 9, and accordingly may have ahigher accuracy, since it is deactivated in the standby mode.

The use of a standby mode of operation reduces the current consumption,but the architecture with the main receiver 10 woken up by the firstreceiver 9, increases the wake up time. Also, the use of two receiversincreases the area of silicon used by the integrated circuit of thenode.

FIG. 4 shows a node in accordance with a first preferred embodiment ofthe present invention. The node comprises a single receiver; thereceiver comprises a high voltage part 20 and a low voltage part 21. Thehigh voltage part 20 comprises voltage to current converters 22 and 23,resistive elements 24 and 25 and a switch 26. These elements need toswing between a voltage close to or equal to V_(SUP) and a voltage closeto ground and accordingly need to be designed with high voltagecomponents; by way of indication, in automotive applications, V_(SUP)may be of the order of 14 volts maximum or 42 volts maximum. The lowvoltage part 21 of the node may use components designed to withstandonly a substantially lower voltage, of the order of 3 to 5 volts, forexample.

The converter 22 is connected to receive a voltage V_(LIN) from thefilter 8, corresponding to the signal 17, and the supply voltage V_(SUP)from the supply terminal 13 and generates a current I_(IN) proportionalto the difference between the voltages (V_(SUP)-V_(LIN)) diminished by asmall gate-source threshold voltage V_(TP). The current I_(IN) isinversely proportional to a resistance R in the converter 22. Thecurrent I_(IN) is passed through the series combination of a fieldeffect transistor (FET) 27 with a resistor 28 of value R₀ and anotherresistor 29 of value R_(HYST). The resistor 29, whose function will beexplained below, is connected between the resistor 28 and the groundterminal 14. The junction of the FET 27 with the resistor 28 is at avoltage V⁻ and is connected by a line 30 to an input of a voltagecomparator 31.

The converter 23 also receives the supply voltage V_(SUP) and isarranged to generate a current I_(SUP) proportional to V_(SUP)diminished by twice the value of the gate-source threshold voltageV_(TP) and inversely proportional to twice the resistance R. The currentI_(SUP) is passed through the switch 26 and then is passed through theseries combination of resistors 32 and 33, similar to the resistors 28and 29, and having the resistance values R₀ and R_(HYST) respectively.The resistor 33 connects one end of the resistor 32 to the groundterminal 14 and the other end of the resistor 32 is connected to supplya voltage V₊ to the second input terminal of the voltage comparator 31.The output of the voltage comparator 31 is supplied to the node outputterminal 15.

The voltage comparator 31 is energised by a supply voltage V_(DD) from aterminal 34 through a switch 35, the voltage V_(DD) being substantiallylower than the voltage V_(SUP) at the terminal 13.

The switches 26 and 35 are actuated by the voltage across the seriescombination of the FET 27 and the resistors 28 and 29 so that as soon asthe current I_(IN) appears, the switches 26 and 35 are closed. In thisway, the quiescent current is at a very low level, but the wake up timeis very short, corresponding to the application of the currents andvoltages to the resistors 32 and 33 and the voltage comparator 31.

In the absence of any hysteresis feedback, the receiver as describedabove, would tend to hover or oscillate between the two output signalvalues in response to small input signal variations or noise when theinput signal level is close to the reference level. To avoid this, theoutput terminal 15 is connected to actuate a bi-stable switch 36 thatalternately connects the junction between resistors 28 and 29 or thejunction between resistors 32 and 33 to the series combination ofresistors 24 and 25, the other end of which is connected to the supplyterminal 13. The value R_(HYST) of the resistors 33 and 29 is chosen tobe small relative to the values of the resistors 24 and 25.

In operation, as shown in FIG. 5, the switch 36 is connected so that, asthe voltage V⁻ increases past the voltage V₊, the switch 36 changes poleto connect the resistors 24 and 25 to the resistor 29 and increasefurther the voltage V⁻, the disconnection of resistors 24 and 25 fromthe resistor 33 simultaneously decreasing the voltage V₊. When thevoltage V⁻ subsequently decreases again past the value of V₊, the switch36 changes pole to connect the resistors 24 and 25 to the resistor 23,decreasing further the voltage V⁻ and increasing the voltage V₊.

A preferred implementation of the receiver shown in FIG. 4 is shown inFIG. 6, where similar elements have similar reference numerals. An npntransistor 37 is connected between the filter 8 and the supply terminal13 and an npn transistor 38 is connected between the filter 8 and theinput to the amplifier 22 the transistors 37 and 38 serving to protectthe rest of the receiver from electrostatic discharge on the LINterminal 7 or the supply terminal 13. The signal from the filter 8 isconnected through the base and emitter of the transistor 37 to a currentsource 39 that limits the current flowing down to ground 14 to 1microamp when the LIN signal is de-asserted at the level of V_(SUP). Theconverter 22 comprises a PMOS FET 40 whose source is connected through aresistor 41 of resistance R to the emitter of transistor 38, whosecollector is connected to the supply terminal 13, its base being shortedto its collector. The junction between the resistor 41 and thetransistor 38 is connected to the emitter of transistor 37. The gate ofFET 40 is connected to the junction between the emitter of transistor 37and the current source 39. The drain of transistor 40 is connected tothe drain of transistor 27, which is an NMOS FET, and whose source isconnected to the resistor 28, its gate being shorted to its drain.

In operation, when the LIN signal at terminal 7 is de-asserted, thevoltage 17 applied to the base of the transistor 37 is close to thesupply voltage V_(SUP) on terminal 13, the transistor 37 is conductive,the voltage on the gate of the FET 40 is also close to that of thesupply terminal 13, and the FET 40 is switched off. When the signal 17at the base of transistor 37 reduces, the voltage at its emitter alsoreduces and once the difference from the voltage V_(SUP) at the terminal13 exceeds the gate-source threshold voltage V_(TP) of the FET 40, theFET 40 begins to conduct. The current flowing in the resistor 41 and theFETs 40 and 27 and the resistors 28 and 29, is proportional to thevoltage across the resistor 41, that is to say the difference betweenthe LIN signal V_(LIN) and the supply voltage V_(SUP) diminished by thethreshold voltage V_(TP) of FET 40.

The junction between the drains of FETs 40 and 27 is connected toactuate the switches 26 and 35 so that, as soon as current flows in theresistors 28 and 29, the resulting voltage closes the switches 26 and35.

The current converter 23 comprises the series combination of tworesistors 42 and 43 each of resistance R and the series combination oftwo resistors 44 and 45, also each of resistance R, in series with theswitch 26 between the terminals 13 and 14. A PMOS FET 46 has its sourceconnected to the junction between resistors 43 and 44, its drainconnected to the resistor 32 and its gate connected to the junctionbetween the resistor 45 and the switch 26, the latter being formed by anNMOS FET.

The operation of the receiver without the hysteresis effect can berepresented by the following equations $\begin{matrix}{{I_{1} = \frac{V_{\sup} - V_{g} - V_{tp}}{2R}};{I_{2} = \frac{V_{tp}}{2R}}} & {{Equation}\quad 1}\end{matrix}$

where I₁ is the current flowing in the resistors 42 and 43 and I₂ is thecurrent flowing in the resistors 44 and 45.

When the receiver is turned on, FET 26 is conductive, connecting thegate of the FET 46 to ground, so that V_(g)=0. $\begin{matrix}{I_{\sup} = {{I_{1} - I_{2}} = {{\frac{V_{\sup} - V_{tp}}{2R} - \frac{V_{tp}}{2R}} = \frac{V_{\sup} - {2V_{tp}}}{2R}}}} & {{Equation}\quad 2}\end{matrix}$

where I_(sup) is the current flowing in the source-drain path of the FET46. $\begin{matrix}{I_{in} = \frac{V_{\sup} - V_{lin} - V_{tp}}{R}} & {{Equation}\quad 3}\end{matrix}$

where I_(in) is the current flowing in the source-drain path of the FET27. $\begin{matrix}{{{V + \frac{V_{\sup}}{2R} - C};{V_{-} = {\frac{V_{\sup} - V_{lin}}{R} - C}}},{{{where}\quad C} = \frac{V_{tp}( {R_{o} + R_{hyst}} )}{R}}} & {{Equation}\quad 4}\end{matrix}$

It follows that, apart from the effect of hysteresis introduced by thefeedback apllied to the resistors 29 and 33, $\begin{matrix}{V_{+} = {{V_{-}\quad{when}\quad V_{lin}} = \frac{V_{\sup}}{2}}} & {{Equation}\quad 5}\end{matrix}$

It will be appreciated that, in the embodiment described above, theconverter 22 generates an input current I_(IN) which is a function ofthe received signal voltage level V_(LIN). The converter 23 generates areference current I_(SUP) that is a function of the reference voltagelevel, the supply voltage V_(SUP) on the terminal 13. The comparator 31responds to the relative values of the voltages generated across theresistors 28 and 29 on one hand and the resistors 32 and 33 on the otherhand by the currents I_(IN) and I_(SUP) respectively. The voltagecomparator 31 is supplied with power at a voltage V_(DD) substantiallylower than the swing in the input signal V_(LIN) between the supplyvoltage V_(SUP) at the terminal 13 and ground at the terminal 14.

The switch 35 renders the comparator 31 selectively operable when thereceived signal V_(LIN) is asserted. Again, the currents I_(SUP) andI_(IN) are generated only when the received signal is asserted.Accordingly the power consumption of this part of the receiver isreduced when the received signal is de-asserted. Voltages developedacross the resistors 28 and 29 on one hand and resistors 32 and 33 onthe other hand are substantially smaller than the swing in the inputsignal voltage level V_(LIN). All these components are included in thelow voltage part 21 of the receiver.

The input current I_(IN) is produced as a function of the relativevoltage levels of the received signal and said input reference voltagelevel. Accordingly, fluctuations in the supply voltage V_(SUP) arecancelled when the input current I_(IN) is compared with the referencecurrent I_(SUP) generated directly from the supply voltage V_(SUP).

FIG. 7 shows another embodiment of the present invention. In theembodiment of FIGS. 4 to 6, the input voltage is compared with thereference voltage by means of a voltage comparator. In the embodiment ofFIG. 7, a current comparator compares the relative values of the inputcurrent I_(IN) and the reference current. In FIG. 7, elements that aresimilar to corresponding elements in FIG. 6 bear similar referencenumerals.

The input voltage to current converter 22 supplies the current I_(IN) toa current mirror 47. The reference voltage to current converter 23supplies the reference current I_(SUP) to a current mirror 48 and,instead of the resistors 44 and 45 of the embodiment of FIG. 6, the gateof the FET 46 is connected to the supply terminal 13 through a currentsource 49 that limits the current to a value I_(G).

The current mirrors 47 and 48 each comprise first and second NMOS FET 50and 51. In each case the current input to the current mirror is passedto the drain terminal of the first FET 50, whose source is connected tothe ground terminal 14 and whose gate is shorted to its drain terminal.The source of the second FET 51 is also connected to the ground terminal14, in each case, and its gate is connected to the gate of therespective first FET 50, its source providing the output current of thecurrent mirror. Compensation current sources 52 and 53 are connected inparallel with the drain-source paths of the FETs 51 of the currentmirrors 47 and 48 respectively to provide compensation currentscorrecting a potential source of inaccuracy in the comparison of thecurrents I_(IN) and I_(SUP). The current source 52 generates a currentequal to V_(TP)/R, where V_(TP) is the gate-source threshold voltage ofthe FETs 40 and 46 and R is the resistance of the resistors 41, 42 and43. The current source 53 generates a current equal to V_(TP)/2R. TheFET 51 of the current mirror 47 produces an output current equal toI_(IN) and, together with the current source 52, passes a current I₂ toa current comparator 54. Similarly, the FET 51 of the current mirror 48produces a current equal to I_(SUP) that, combined with the current fromcurrent source 53, passes a current I₁ to the current comparator 54.

The current comparator 54 comprises a first PMOS FET 55 whose source isconnected to the low voltage supply terminal 34 and whose drain isconnected to receive the current I₂ from the current mirror 47. Thecurrent comparator 54 also comprises a PMOS FET 56 whose source isconnected to the low voltage supply terminal 34 and whose drain isconnected to receive the current I₁ from the current mirror 48. The gateof the FET 56 is shorted to its drain and the gates of FETs 55 and 56are connected together.

In operation, when the input signal on the terminal 7 is de-asserted,the difference between the supply voltage on the terminal 13 and thevoltage level V_(LIN) from the filter 8 is smaller than the source gatethreshold voltage V_(VT) of the FET 40, so that the current I_(IN) is 0and the current I₂ is also substantially 0. The FET 26 is turned off sothat the voltage of the gate of the FET 46 rises to the supply voltageV_(SUP) of the terminal 13 and the FET 46 is also turned off.

As the input voltage V_(LIN) reduces, the current I_(IN) starts toincrease and the FETs 26 and 46 are turned on. As long as the current I₂remains smaller than the current l₁, the FET 55 is maintained conductiveand the voltage at the junction between the drains of the FET 55 and theFET 51 of the current mirror 47 is close to the low voltage supply ofterminal 34. When the current I₂ exceeds the current I₁, the FET 55 isturned off and the FET 56 is turned on, the voltage at the junctionsbetween FET 55 and current mirror 47 falling close to the groundterminal 14.

Hysteresis is provided by an inverter 57, the output of the inverter 57being supplied to the node output terminal 15 through an output inverter58. The output of inverter 57 is connected to the gate of a PMOS FET 59,whose source is connected to the drain of FET 55. The drain of FET 59 isconnected to the drain of a PMOS FET 60 whose source is connected to thelow voltage terminal 34. The gate of FET 60 is connected to the gates ofFETs 55 and 56.

A source of a small current I_(SET) is connected across the source anddrain of the FET 55, to provide a current at the start of the circuit.

The operation of the receiver without the hysteresis effect can berepresented by the following equations $\begin{matrix}{{I_{in} = \frac{V_{\sup} - V_{lin} - V_{tp}}{R}};{I_{\sup} = \frac{V_{\sup} - V_{g} - V_{tp}}{2R}};{I_{vt} = \frac{V_{tp}}{R}}} & {{Equation}\quad 6}\end{matrix}$

where I_(vt) is the current in the source 52. $\begin{matrix}{{I_{1} = \frac{V_{\sup}}{2R}};{I_{2} = \frac{V_{\sup} - V_{lin}}{R}}} & {{Equation}\quad 7}\end{matrix}$

It follows that, apart from the effect of hysteresis introduced by thefeedback applied to the resistors 29 and 33, I₂=I₁ when $\begin{matrix}{{\frac{V_{\sup} - V_{lin}}{R} = \frac{V_{\sup}}{R}};{V_{lin} = \frac{V_{\sup}}{2}}} & {{Equation}\quad 8}\end{matrix}$

1. A receiver for receiving a switched signal on a communication line,said signal varying between first and second voltage levels, saidreceiver comprising comparator means responsive to the relative valuesof the received signal voltage level and an input reference voltagelevel, characterised in that said comparator means comprises currentgenerating means selectively operable when said received signal isasserted to produce an input current which is a function of saidreceived signal voltage level and a reference current which is afunction of said input reference voltage level, and output meansresponsive to the relative values of said input current and saidreference current, said output means being supplied with power at avoltage substantially lower than the difference between said first andsecond voltage levels, and said comparator means being responsive tosaid received signal to reduce its power consumption when said receivedsignal is de-asserted.
 2. A receiver as claimed in claim 1, wherein saidoutput means is selectively operable when said received signal isasserted.
 3. A receiver as claimed in claim 1, wherein said comparatormeans comprises switch means responsive to said input current forreducing the power consumption of said comparator means when saidreceived signal is de-asserted.
 4. A receiver as claimed in claim 1,wherein said received signal voltage level is substantially equal tosaid input reference voltage when the received signal de-asserted and isrelatively small when the received signal asserted.
 5. A receiver asclaimed in claim 1, wherein said current generating means is arranged toproduce said input current as a function of the relative voltage levelsof the received signal and said input reference voltage level when saidreceived signal is asserted.
 6. A receiver as claimed in claim 1,wherein said current generating means comprises an input stage includinga current limiter in series with a current amplifier element thatpresents a high impedance when said received signal is asserted, and aninput signal converter stage for passing said input current as afunction of said received signal voltage level when said received signalis asserted.
 7. A receiver as claimed in claim 6, wherein said inputsignal converter stage comprises a resistive element and said inputstage is arranged to apply a voltage which is a function of thedifference between said received signal voltage level and said inputreference voltage level across said resistive element when said receivedsignal is asserted.
 8. A receiver as claimed in claim 7, wherein saidcurrent generating means comprises a reference converter stage forpassing said reference current as a function of said input referencevoltage level when said received signal is asserted, said referenceconverter stage comprising a resistive element across which said inputreference voltage level is applied when said received signal isasserted.
 9. A receiver as claimed in claim 8, wherein said input signalconverter stage and said reference converter stage present similarthreshold voltages that modify the voltages applied across saidresistive elements.
 10. A receiver as claimed in claim 1, wherein saidoutput means comprises comparator resistive elements for receiving saidinput current and said reference current respectively and voltagecomparator means responsive to the relative values of the voltagesdeveloped across said comparator resistive elements, the voltagesdeveloped across said comparator resistive elements being substantiallysmaller than the difference between said first and second voltagelevels.
 11. A receiver as claimed in claim 1, wherein said output meanscomprises current comparator means responsive to the relative values ofsaid input current and said reference current, the voltages developed insaid current comparator means being substantially smaller than thedifference between said first and second voltage levels.
 12. A receiveras claimed in claim 1, wherein said output means comprises hysteresismeans for modifying the response of said output means to said relativevalues, whereby to avoid oscillation of said comparator means inresponse to a small change in input.